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A class of systematic t/B-error correcting codes for semiconductor memory systems

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2 Author(s)
Umanesan, G. ; Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan ; Fujiwara, E.

This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (StB/EC-SbEC-SBED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures

Published in:

Information Theory Workshop, 2001. Proceedings. 2001 IEEE

Date of Conference: