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An area-efficient iterative modified-Booth multiplier based on self-timed clocking

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3 Author(s)
Myoung-Cheol Shin ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Se-Hyeon Kang ; In-Cheol Park

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64×64-bit multiplication

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Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

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