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An analytical model for trace cache instruction fetch performance

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2 Author(s)
Hossain, A. ; Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA ; Pease, D.J.

This paper presents an analytical model of instruction fetch performance of a trace cache. This paper also presents an analytical model of miss rate of a trace cache. These models can be used to analyze performance and behavior of a microarchitecture of a processor. These models are implemented in a new microarchitecture tool Tulip. Performances of several benchmark programs based on Tulip are also presented in this paper

Published in:

Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

Date of Conference:

2001