By Topic

An analytical model for trace cache instruction fetch performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hossain, A. ; Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA ; Pease, D.J.

This paper presents an analytical model of instruction fetch performance of a trace cache. This paper also presents an analytical model of miss rate of a trace cache. These models can be used to analyze performance and behavior of a microarchitecture of a processor. These models are implemented in a new microarchitecture tool Tulip. Performances of several benchmark programs based on Tulip are also presented in this paper

Published in:

Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

Date of Conference: