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Realization of multiple-output functions by reconfigurable cascades

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3 Author(s)
Iguchi, Y. ; Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan ; Sasao, T. ; Matsuura, M.

A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). Finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA. This realization uses time domain multiplexing, and is useful for the case where the number of output pins is limited

Published in:

Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

Date of Conference:

2001

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