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A hierarchical simulation framework for application development on system-on-chip architectures

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2 Author(s)
Mathur, V. ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Prasanna, V.K.

We propose a hierarchical simulation methodology to assist application development on System-on-Chip architectures. Hierarchical simulation involves simulation of a SoC based system at different levels of abstraction. Thus, it enables a system designer to exploit simulation speed vs. accuracy of results trade-offs. Vertical simulation is a special case of hierarchical simulation, where a feedback mechanism between the different simulation levels helps in "interpreting" the results of stand-alone simulations in the system-wide context. The paper presents an approach to perform vertical simulation of a class of applications under a simplified scenario

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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