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IP protection for VLSI designs via watermarking of routes

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5 Author(s)
Narayan, N. ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; Newbould, R.D. ; Carothers, J.D. ; Rodriguez, J.J.
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Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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