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CID/DRAM mixed-signal parallel distributed array processor

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2 Author(s)
Genov, R. ; Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA ; Cauwenberghs, G.

Presents a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512×128 vector-matrix multiplier on a single 3 mm×3 mm chip fabricated in standard CMOS 0.5 μm technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001