CID/DRAM mixed-signal parallel distributed array processor

Presents a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512/spl times/128 vector-matrix multiplier on a single 3 mm/spl times/3 mm chip fabricated in standard CMOS 0.5 /spl mu/m technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate.