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An efficient digit-serial systolic multiplier for finite fields GF(2m)

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3 Author(s)
Chang Hoon Kim ; Dept. of Comput. & Inf. Eng., Taegu Univ., Kyungbuk, South Korea ; Sang Duk Han ; Chun Pyo Hong

An efficient digit-serial systolic array is proposed for multiplication in finite fields GF(2m) with the standard basis representation. From the least significant bit first algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data comes in continuously, the proposed array can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a considerable reduction of computational delay time with a moderate increase of hardware complexity, compared to the existing digit-serial systolic multipliers. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation with fault-tolerant design

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001