An efficient digit-serial systolic multiplier for finite fields GF(2/sup m/)

An efficient digit-serial systolic array is proposed for multiplication in finite fields GF(2/sup m/) with the standard basis representation. From the least significant bit first algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data comes in continuously, the proposed array can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a considerable reduction of computational delay time with a moderate increase of hardware complexity, compared to the existing digit-serial systolic multipliers. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation with fault-tolerant design.