By Topic

A unified validation methodology for system level co-design and co-implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

Describes a validation centric approach to the design architecting and implementation of System on Chip solutions. The proposed methodology allows an Integrator to rapidly utilise pre-defined IP objects consisting of both hardware, software and validation components which are structured in such as way as to minimise the effort in systems validation., Moreover the methodology tackles the issue of implementation certification once a suitable HW/SW partition has been selected. Current research using contemporary tool chains is used to illustrate the methodology

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001