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Modular scalable parallel architectures for fast transforms

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3 Author(s)
Johnson, R.W. ; MathStar Inc., Minneapolis, MN, USA ; Koyrakh, L.A. ; Pihl, D.M.

Using a new approach, hardware interpretation of mathematical expressions, we derive modular scalable parallel hardware architectures for fast transforms in the mathematically rigorous way. The approach is built on the observation that computer memory addresses, when written in bit representation resemble multidimensional tensor indices. Therefore, it is possible to describe computer architectures using tensor algebra in the multidimensional space, in which each dimension is described by its bit on the memory bus. In this picture the transforms performed by the hardware architecture can be described as tensor transformations. Tensor algebra therefore is the natural language to use in computer science. It allows one to describe important signals, components, their interaction, derive instructions and help to perform other design tasks. As an example we present a derivation of a modular, fully scalable, maximally parallel with maximal data reuse FFT hardware architecture. Presented ideas could be applied to building hardware for other transforms as well (DCT, wavelet and so on)

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001