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An embedded programmable core for the implementation of high performance digital filters

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2 Author(s)
B. I. Hounsell ; Dept. of Electr. Eng., Edinburgh Univ., UK ; T. Arslan

This paper presents a novel, embedded programmable logic array (PLA) for implementing high performance filter functions. A custom-built configurable architecture together with a fast and local interconnect hierarchy, provides a high degree of flexibility for realisation of a given filter specification. The PLA is designed to be reconfigured with external hardware or software all in a system-on-chip platform. A stochastic algorithm is used in this paper to demonstrate the automated configuration of the PLA architecture for a practical filter example. The highly parallel nature of the PLA architecture ensures scalability for complex filter tasks, and provides a highly fault tolerant platform for embedded filter applications. Investigations show that even when 20% of the PLA architecture is damaged the same filter example can still be successfully implemented. Further results demonstrate the scalability, speed, and array utilisation of the architecture using a typical SoC bus specification

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: