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A new two-layer power/ground router for VLSI layout

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2 Author(s)
Jun-Cheng Chi ; Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan ; Mely Chen Chi

The authors present a new router which can be used to route power and ground nets through the use of double metal layers. It was developed for integrated circuit designs. A chip may have multiple power/ground pads located on any side of the chip. Multiple trees may be constructed for power or ground nets to consume as small as possible routing resource. The routing algorithm used is a modification of Dijkstra's algorithm, which searches for the shortest path between a pin and a pad. It uses a new metric for the cost function. The cost is the total area of routing wires and the additional pitch region due to the routing path. Corner reduction is also considered. This new metric is more accurate in measuring the quality of routing than wire length/area alone because the reserved pitch region may not be used for routing any other net. The power and ground nets are routed under the constraints of electromigration and voltage drop of the chip. Experimental results are shown

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: