By Topic

Algorithm, architecture, and implementation of algorithmic delay-locked loop based data recovery circuit for high-speed serial data communication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Hongjiang Song ; Intel Corp., Chandler, AZ, USA

An algorithmic delay-locked loop (DLL) based high-speed serial data recovery circuit (DRC) architecture is proposed. This scheme is based on a novel modulator-based phase synthesis and phase error compensation principle, which offers advantages of inherently instantaneous locking capability, high jitter tolerance, and unconditional loop stability. Its fully digital, highly regular, modular, and scaleable VLSI implementations is very suitable for the SoC solution to various high-speed, low power applications. The architecture has been implemented in test chips fabricated using a 0.25 μm standard CMOS process technology. It occupied the area around 300 μm × 150 μm, consumed less than 4 mW power. It demonstrated higher than 800 Mb/s data rate, and a better than 10-9 BER at 480 Mb/s rate and the best measured BER of better than 10-12 with a 215-1 pseudorandom data stream across a USB cable

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001