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Code verification by hardware acceleration

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4 Author(s)
Kohler, H. ; IBM Lab., Boeblingen, Germany ; Kayser, J. ; Pape, H. ; Ruffner, H.

Presents the IML-code-verification methodology used for virtual poweron of IBM's high end servers. Virtual poweron is the process to verify, the IML (initial micro program) code weeks before the realhardware prototype is available. "Virtual-hardware" consisting of a simulation model loaded into a hardware accelerator box and a program connecting the service-element to the hardware accelerator is used instead

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: