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Performance evaluation of 3rd order sigma-delta (Σ-▵) modulators via FPGA implementation

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2 Author(s)
Abeysekera, S.S. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore ; Charoensak, C.

Sigma-delta (Σ-▵) modulators have been widely used over the last few decades, in various signal processing applications. Usually, for improved signal-to-noise (quantization) performances, higher order modulators are utilized in these applications. In this paper, we investigate the performance of third order Sigma-delta (Σ-▵) modulators and corresponding demodulators via Field Programmable Gate Array (FPGA) implementations. Two modulator architectures, the multi-stage (MASH) Σ-▵ architecture and the Look Ahead Decision Feedback (LADF) Σ-▵ architecture are compared on their performances. It is shown that the LADF Σ-▵ architecture, which has not been widely reported in the literature, is preferable over the other modulators in the design of Σ-▵ modulators. The selection of demodulator filters for reducing quantization noise resulting from the MASH and LADF Σ-▵ architectures is also addressed in the paper. Advantages and disadvantages of various demodulator filters, e.g. sinc filters and recursive filters are discussed via the FPGA implementation

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001