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VLSI implementation of high performance burst mode for 128-bit block ciphers

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4 Author(s)
Y. Mitsuyama ; Dept. of Inf. Syst. Eng, Osaka Univ., Japan ; Z. Andales ; T. Onoye ; I. Shirakawa

A new cipher mode, called the burst mode, is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 times of block cipher encryptions. Experimental results show that the VLSI implementation of the burst mode with the use of a hardware accelerator, where AES is performed by software, raises the speed of the software implementation by four times, achieving the maximum rate of 1.3 Gbps

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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