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Power estimation in adiabatic circuits: a simple and accurate model

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2 Author(s)
Alioto, M. ; Dept. of Electr. Electron. & Syst., Catania Univ., Italy ; Palumbo, G.

A simple procedure to evaluate the energy consumption of adiabatic gate circuits is proposed and validated. The proposed strategy is based on a linearization of the circuit and simplifying the analytical result obtained on the equivalent network. The approach leads to simple relationships which can be used for a pencil-and-paper evaluation or implemented on software. The accuracy of the results is validated by means of Spice simulations on an adiabatic full adder designed with a 0.8 /spl mu/m technology.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 5 )