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An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration

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2 Author(s)
Jun Ming ; California Univ., Davis, CA, USA ; Lewis, S.H.

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm 2 in a single-poly 0.5 μm CMOS technology

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Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 10 )