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An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm 2 in a single-poly 0.5 μm CMOS technology
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:36
,
Issue:
10
)
Date of Publication: Oct 2001
- Page(s):
- 1489 - 1497
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7065248
- Digital Object Identifier :
- 10.1109/4.953477
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Oct 2001
- Sponsored by :
- IEEE Solid-State Circuits Society
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