By Topic

Communication architectures for system-on-chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. E. Kreutz ; Fed. Univ. of Rio Grande do Sul, Brazil ; L. Carro ; C. A. Zeferino ; A. A. Susin

The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip (SoC) devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most crucial factor to meet design constraints. This goal of this work is to define and implement algorithms devoted to analyzing and selecting those communication architectures that better match the user defined system constraints, in an integrated design environment

Published in:

Integrated Circuits and Systems Design, 2001, 14th Symposium on.

Date of Conference:

2001