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Minimizing area/energy for low power memory design using integer linear programming

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1 Author(s)
Wen-Tsong Shiue ; Syst. Level Design, Motorola Inc., Austin, TX, USA

In this paper we describe a multi-module, multiport memory design procedure that satisfies area and/or energy constraints, in addition to the cycle budget. We show how loop transformations can be used to derive architectures with fewer memory modules and fewer memory ports. We develop ILP-based models (to obtain optimal solutions) to determine the memory configuration for the case when (i) area has to be minimized, given the energy bound, (ii) energy has to be minimized, given the area bound

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Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on  (Volume:2 )

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