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Low power binding using linear programming

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3 Author(s)
Wen-Tsong Shiue ; Syst. Level Design, Motorola Inc., Austin, TX, USA ; Denison, J. ; Horak, A.

This paper outlines a novel approach to low power binding in high level synthesis based on linear programming methods. In order to using linear programming (LP), we first map the binding problem to a graph called a parallel graph (PG). Once the PG is created, linear programming techniques are used to search all paths through the PG to find the optimal binding that minimizes the overall power consumption due to switching activity. We benchmarked our algorithm on two applications, a second-order differential equation solver (DiffEq) and a finite impulse response filter (FIR). In our experiments, the power consumption of the DiffEq was reduced by 8.2%. Power consumption for a FIR filter sharing three multipliers and three adders was reduced by 18.5% while the same FIR sharing two multipliers and two adders achieved a 32.2% power reduction

Published in:
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on  (Volume:2 )

Date of Conference: 2000

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