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A 3.3 V 10 bit current-mode folding and interpolating CMOS A/D converter using an arithmetic functionality

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4 Author(s)
Jin-Won Chung ; Dept. of Electron. Eng., Inha Univ., Inchon, South Korea ; Hwa-Yeal Yu ; Se-Hoon Oh ; Kwang-sub Yoon

A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 μm n-well CMOS double poly/three metal process. The simulation result shows a differential nonlinearity (DNL) of -0.5 LSB, an integral nonlinearity (INL) of -1.0 LSB

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Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on  (Volume:2 )

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