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Fingerprinting techniques for field-programmable gate array intellectual property protection

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3 Author(s)
J. Lach ; Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA ; W. H. Mangione-Smith ; M. Potkonjak

As current computer-aided design (CAD) tool and very large scale integration technology capabilities create a new market of reusable digital designs, the economic viability of this new core-based design paradigm is pending on the development of techniques for intellectual property protection. This work presents the first technique that leverages the unique characteristics of field-programmable gate arrays (FPGAs) to protect commercial investment in intellectual property through fingerprinting. A hidden encrypted mark is embedded into the physical layout of a digital circuit when it is placed and routed onto the FPGA. This mark uniquely identifies both the circuit origin and original circuit recipient, yet is difficult to detect and/or remove, even via recipient collusion. While this approach imposes additional constraints on the backend CAD tools for circuit place and route, experiments indicate that the performance and area impacts are minimal

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:20 ,  Issue: 10 )