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A high throughput FPGA implementation of a bit-level matrix-matrix product

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4 Author(s)
Amira, A. ; Sch. of Comput. Sci., Queen''s Univ., Belfast, UK ; Bouridane, A. ; Milligan, P. ; Sage, P.

This paper presents a novel architecture for a matrix-matrix multiplication algorithm. The paper describes the mathematical model for the algorithm (based on Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation requiring (N2) and O(2nN) as area and time complexities respectively, where N is the matrix size and n is the word length

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Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on  (Volume:1 )

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