Optimized speaker independent speech recognition system for low cost application

Describes an ASIC design and implementation of 15-isolated-word, speaker independent speech recognition system for low cost application. The input to the IC is a 12-bit sample with a sampling rate of 11.025 kHz. The delay between the end of a word and the response from the IC is approximately 0.24s. The IC runs at 10 MHz system clock and is targeted at 0.35 /spl mu/m CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM, contains about 61000 gate counts. The core die size is 1.5mm/spl times/3mm. The current design was simulated in VHDL for hardware implementation and the functionality of the IC was identical to the MATLAB simulation. The system achieves a recognition rate of 89% for the 15 isolated words.