Referenced Items are not available for this document.
RNS architectures to compute the orthogonal DWT and its inverse are shown. The relation between the coefficients of the analysis and synthesis filters allows one to halve the number of required LUTs and modular adders. Simulations of one- and two- octave implementations using VHDL and FPL devices show a performance advantage of up to 23.45 and 96.58% when compared to the 2's complement arithmetic versions, respectively
Published in:
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
(Volume:3
)
Date of Conference: 2000
- Page(s):
- 1170 - 1173 vol.3
- Meeting Date :
- 08 Aug 2000-11 Aug 2000
- Print ISBN:
- 0-7803-6475-9
- INSPEC Accession Number:
- 7168080
- Conference Location :
- Lansing, MI
- Digital Object Identifier :
- 10.1109/MWSCAS.2000.951423
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
