By Topic

Damping controller design for FACTS device. II. Controller structure and parameter optimisation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
C. Y. Chung ; Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada ; C. T. Tse ; C. K. Cheung ; C. W. Yu
more authors

A new approach to solve the instability problem, due to the interaction between the damping controller and FACTS thyristor circuit, is introduced. FACTS instability mode is detected in the design process so the structure and setting of the damping controller is achieved through a combined sensitivity coefficient (CSC) which automatically takes into account the damping of both the interarea and FACTS modes. Traditionally, a lead/lag circuit is regarded as providing phase compensation for a controller so a few lead/lag stages would be needed to achieve sufficient phase shifts at the frequency of concern. In this paper, however, a different viewpoint is offered. From time constant synthesis, three different objectives of a proper designed lead/lag circuit are highlighted, but the dominant one is associated with gain compensation, not with phase compensation. Moreover, the required number of stages, the choice of lead or lag compensation, and the selection of the time setting ranges are all clearly indicated from the synthesis.

Published in:

Advances in Power System Control, Operation and Management, 2000. APSCOM-00. 2000 International Conference on  (Volume:2 )

Date of Conference:

30 Oct.-1 Nov. 2000