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Cached DRAM for ILP processor memory access latency reduction

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3 Author(s)
Z. Zhang ; Coll. of William & Mary, Williamsburg, VA, USA ; Z. Zhu ; X. Zhang

Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors

Published in:

IEEE Micro  (Volume:21 ,  Issue: 4 )