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Reliability monitoring and screening issues with ultrathin gate dielectric devices

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1 Author(s)
W. W. Abadeer ; Microelectron. Div., IBM Corp., Essex Junction, VT, USA

Installing appropriate quality and reliability monitoring procedures for ultrathin gate dielectrics is of utmost importance. Ensuring the integrity of VLSI products and unwavering customer satisfaction are the top priorities. Several key strategic avenues have been pursued to accomplish those priorities. First, basic tool and processing monitoring and measurement procedures are put into place for categories such as metallic contamination, foreign material control, and semiconductor stress-induced defects such as dislocations and stacking faults. Second, a new voltage ramp breakdown test, especially designed for ultrathin gate dielectrics, is installed based on a one-to-one correlation with TDDB testing, from which a fail criterion for minimum required breakdown voltage of the distribution is defined. The voltage ramp test is capable of identifying weaknesses or failures for either the intrinsic or extrinsic parts of the failure rate distribution. The voltage ramp test is installed at various processing levels starting with post silicide probing (PSP) utilizing very large guide area/perimeter structures (area>0.5 mm2/chip, and perimeter >1 meter/chip) with both shallow trench isolation (STI) and diffusion perimeters. Third, a voltage breakdown test is put into place for in-line charging effects at various processing levels. The structure used employs minimum polysilicon linewidth devices and contains a nonantenna reference device as well as a variety of antenna structures for various design levels starting with polysilicon and including all via, contact, and metal levels. Such a dielectric breakdown test for charging is also well correlated with other device failure mechanisms such as hot carriers. Fourth, a new methodology was adopted based on a one-to-one quantitative correlation between lifetime as derived from accelerated TDDB testing and the initial value of gate dielectric leakage at a predetermined value(s) of voltage(s). This excellent correlation was verified for gate dielectric thickness ranging from 10 nm to below 3 nm. Fifth, at product level, the standby IddQ and Idd currents are measured and tracked for changes under accelerated stress conditions for numerous scan chains. This measurement is a good indicator of the defect level on products and the overall impact of ultrathin gate dielectric on product yield and reliability. Finally, various types of voltage screens and burn-in with duration ranging from few seconds to several hours (at wafer and packaged levels) can be implemented (at least on a selected set of products) to monitor and/ improve the reliability of the final assembly. Accordingly, the body of the text discusses the following topics: monitoring of gate dielectric reliability, monitoring of device stability, monitoring of thin dielectric initial leakage, semiconductor stress induced defects, metallic contamination, and reliability of integrated circuits

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IEEE Transactions on Device and Materials Reliability  (Volume:1 ,  Issue: 1 )