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Design methodology and optimization strategy for dual-VTH scheme using commercially available tools

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3 Author(s)
Hirabayashi, M. ; Inst. of Ind. Sci., Tokyo Univ., Japan ; Nose, K. ; Sakurai, T.

Design methodology for dual-VTH scheme using commercially available tools is presented and optimization strategy for the dual-VTH scheme is discussed. In order to suppress the power consumption, it is shown that using library cells that have various combinations of VTH's is not needed. The cell library, which contains logic gates with all high VTH transistors and all low VTH transistors, is sufficient to reduce leakage power. 0.1 V is shown to be the optimum value for VTH difference between VTH,HIGH and VTH,LOW in terms of power reduction

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Low Power Electronics and Design, International Symposium on, 2001.

Date of Conference: