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Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors

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3 Author(s)
Chung-Hsing Hsu ; Dept. of Comput. Sci., Rutgers Univ., NJ, USA ; U. Kremer ; M. Hsiao

Dynamic voltage and frequency scaling of the CPU has been identified as one of the most effective ways to reduce energy consumption of a program. This paper discusses a compilation strategy that identifies scaling opportunities without significant overall performance penalty. Simulation results show CPU energy savings of 3.97%-23.75% for the SPECfp95 benchmark suite with a performance penalty of at most 2.53%

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Low Power Electronics and Design, International Symposium on, 2001.

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