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Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping

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2 Author(s)
Cong, J. ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Yean-Yow Hwang

In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array (FPGA) technology mapping. Our Boolean matching methods, which are based on functional decomposition operations, can characterize functions for complex PLBs consisting of multiple LUTs (possibly of different sizes) such as Xilinx XC4K CLBs. With these techniques, we conducted quantitative evaluation of four PLB architectures on their functional capabilities. Architecture evaluation results show that the XC4K CLB can implement 98% of six-input and 88% of seven-input functions extracted from MCNC benchmarks, while a simplified PLB architecture is more cost effective in terms of function implementation per LUT bit. Finally, we proposed new technology mapping algorithms that integrate Boolean matching and functional decomposition operations for depth minimization. Technology mapping results show that our PLB mapping approach achieves 12% smaller depth or 15% smaller area in XC5200 FPGAs and 18% smaller depth in XC4K FPGAs, compared to conventional LUT mapping approaches

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:20 ,  Issue: 9 )