By Topic

An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Jaganathan, S. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Krishnan, S. ; Mensa, Dino ; Mathew, T.
more authors

We report an 18-GHz clock-rate second-order continuous-time Σ-Δ analog-digital converter (ADC) implemented using InP-transferred substrate HBTs. Under two-tone test conditions, the ADC achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The IC occupied 1.95 mm2 die area and dissipated ~1.5 W

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 9 )