Referenced Items are not available for this document.
A novel design methodology for the implementation of control units for application specific instruction set processors (ASIPS) is described. This methodology uses automatic instruction encoding and semi-automatic generation of the hardware instruction decoder to speed up the ASIP design. Significant power savings due to optimized instruction encoding are achieved. Results for ICORE (ISS-Core), which is an ASIP for digital video broadcasting algorithms of Infineon Technologies, demonstrate the efficiency and applicability of this approach
Published in:
Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on
(Volume:2
)
Date of Conference: 2001
- Page(s):
- 1169 - 1172 vol.2
- Meeting Date :
- 07 May 2001-11 May 2001
- ISSN :
- 1520-6149
- Print ISBN:
- 0-7803-7041-4
- INSPEC Accession Number:
- 7128445
- Conference Location :
- Salt Lake City, UT
- Digital Object Identifier :
- 10.1109/ICASSP.2001.941131
- Product Type:
- Conference Publications
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