DSP data path synthesis for low-power applications

We present a high-level synthesis technique targeting low power consumption for data-dominated applications. We have used a statistical estimation technique to obtain the switching activity of modules when sharing of computing resources are required in a design. The technique enables us to understand the switching behavior under resource sharing. Using the relationship between switching power and resource sharing thus obtained, we developed scheduling and allocation algorithms to reduce the data path switching power. Experiments performed on various examples show up to 49% improvement in power reduction under resource constraints