Referenced Items are not available for this document.
For the future system on chip era, the embedded DRAM is one of the most important devices. Since the kinds of device increase and each device must be produced from only 10000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as little as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08 μm trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 μm trench to 80% of 0.18-μm trench, with an investment of only $1.6 M. It is achieved by the LOCOS collar process and HSG technique
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:14
,
Issue:
3
)
Date of Publication: Aug 2001
- Page(s):
- 196 - 201
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 7016021
- Digital Object Identifier :
- 10.1109/66.939812
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Aug 2001
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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