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Asynchronous cross-pipelined multiplier

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4 Author(s)
J. Butas ; Dept. of Electr. Eng., Chinese Univ. of Hong Kong, Shatin, China ; Chiu-Sing Choy ; J. Povazanec ; Cheong-Fat Chan

In this paper, a design of a 16-bit asynchronous multiplier is presented. The multiplier core consists of small basic blocks. Each block includes handshake and computation logic and communicates with four neighbor cells in asynchronous handshake fashion using four-phase protocol. The computation logic is implemented in dual-rail coded domino logic. The input and output signals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four-phase signaling. The design speed is self-adjusting to the technology parameters and supply voltage variations. The multiplier has low latency and achieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6-μm CMOS process and has a core size of 4.3×2.1 mm

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 8 )