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An algorithm for computing AB2+C over a finite field GF(2m) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems
Published in:
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
(Volume:48
,
Issue:
5
)
Date of Publication: May 2001
- Page(s):
- 519 - 523
- ISSN :
- 1057-7130
- INSPEC Accession Number:
- 7016470
- Digital Object Identifier :
- 10.1109/82.938363
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 August 2002
- Issue Date :
- May 2001
- Sponsored by :
- IEEE Circuits and Systems Society
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