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Model checking has become a widely used technique for formal verification of concurrent systems, such as communication protocols. However its rise is still much restricted to scientists with high mathematical education because temporal logic formulae are difficult to understand and even more difficult to create. Therefore, many projects have been started to find out how computers can help engineers in specifying system properties. This paper reports on using patterns of temporal logic formulae, which facilitate the usage of model checking.
EUROCON'2001, Trends in Communications, International Conference on. (Volume:2 )
Date of Conference: 4-7 July 2001