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On-line error detection techniques for dependable embedded processors with high complexity

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3 Author(s)
M. Pfanz ; Comput. Eng. Dept., BTU, Cottbus, Germany ; K. Walther ; H. T. Vierhaus

Presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the cross-parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors

Published in:

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Date of Conference: