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A two-dimensional, distributed logic architecture

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2 Author(s)
M. J. Irwin ; Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA ; R. M. Owens

The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative memory processors, this architecture uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which can be solved very efficiently on the proposed architecture

Published in:

IEEE Transactions on Computers  (Volume:40 ,  Issue: 10 )