Cart (Loading....) | Create Account
Close category search window
 

RF-CMOS performance trends

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed

Published in:

Electron Devices, IEEE Transactions on  (Volume:48 ,  Issue: 8 )

Date of Publication:

Aug 2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.