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Design and development paradigm for industrial formal verification CAD tools

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4 Author(s)
Krishnamurthy, N. ; Motorola Inc., Austin, TX, USA ; Abadir, M.S. ; Martin, A.K. ; Abraham, J.A.

CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve. This article discusses a few fundamental design decisions behind the successful deployment of a second-generation formal custom-memory equivalence-checking tool, Versys2, in the PowerPC design flows. The Versys2 symbolic simulator was developed at Motorola for verifying equivalence between register-transfer-level (RTL) designs and custom transistor circuit schematics

Published in:

Design & Test of Computers, IEEE  (Volume:18 ,  Issue: 4 )