Referenced Items are not available for this document.
The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology
Published in:
Design & Test of Computers, IEEE
(Volume:18
,
Issue:
4
)
Date of Publication: Jul/Aug 2001
- Page(s):
- 6 - 15
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 7014815
- Digital Object Identifier :
- 10.1109/54.936244
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 August 2002
- Issue Date :
- Jul/Aug 2001
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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