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40-Gbit/s D-type flip-flop and multiplexer circuits using InP HEMT

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7 Author(s)
Suzuki, T. ; Fujitsu Labs. Ltd., Atsugi, Japan ; Kano, H. ; Nakasha, Y. ; Takahashi, T.
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We developed a novel design technique for a D-type flip-flop (D- FF) circuit that is based on a small-signal-equivalent circuit approach. This technique provides the best condition to operate the D-FF at a high frequency. Using this technique, we fabricated a master-slave D-FF using a 0.15-/spl mu/m InP HEMT technology. We achieved 40-Gbit/s operation with clear-eye-waveform patterns and reduced jitter.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2001. Digest of Papers. 2001 IEEE

Date of Conference:

20-22 May 2001