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Route packets, not wires: on-chip interconnection networks

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2 Author(s)
Dally, W.J. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Towles, B.

Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference: