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VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

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3 Author(s)
Janiszewski, I. ; Fachbereich Elektrotechnik, FH Darmstadt, Germany ; Hoppe, B. ; Meuth, H.

Design methodologies for high performance direct digital frequency synthesizers (DDFS) are described. Traditional look-up tables (LUT) for sine and cosine are merged with CORDIC-interpolation into a hybrid architecture. This implements DDFS-systems with high resolution without being specific to a particular target technology. Amplitude constants were obtained from mathematical trigonometric functions of the IEEE math_real package. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizer's inherent parameters lead to a design optimum of the LUT/CORDIC-ratio, which minimizes power and silicon area for a given clock frequency.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference:

2001