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A 1.0 Gb/s BiCMOS multi-channel optical interface transmitter and receiver chip set for high resolution digital displays

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5 Author(s)
Gun Sang Lee ; Dept. of Electron. Eng., Korea Univ., Seoul, South Korea ; Yong Sub Kim ; Jae Hun Lee ; Doo Hwan CHoi
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In this paper, a 1.0 Gb/s multi-channel optical interface transmitter (Tx) and receiver (Rx) chip set is presented. For a high resolution liquid crystal display (LCD) operating up to SXGA (1280×1024) pixels) grade, we present a high speed serial digital video I/O scheme with low EMI, skew-tolerant and long transmission distance. The interface chip set has a data recovery system with ±1 bit skew compensation and a 8B9B encoding/9B8B decoding for dc balancing. The analog front ends of the optical interface such as laser driver in Tx and PD current detector in Rx are fully integrated in the chip set. The Tx consists of an encoder, a pipelined high speed serializer, and a vertical cavity surface emitting laser (VCSEL) driver. The Rx consists of a transimpedance amplifier for PD input, a deserializer, and a decoder for each channel. Fully integrated low jitter PLLs are implemented for clocking in the chip set. With a single 2.5 V supply operating at 1.0 Gb/s, the power consumption of the Tx is 150 mW and that of the Rx is 230 mW. They were implemented in a 0.5 um, 3-metal BiCMOS process and occupy an active area of 3,170*3,440 mm2 each

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Consumer Electronics, 2001. ICCE. International Conference on

Date of Conference: