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Path metric memory management for minimising interconnections in Viterbi decoders

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3 Author(s)
S. -Y. Kim ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; H. Kim ; I. -C. Park

To simplify the interconnection between processing elements and path metric memory banks in Viterbi decoders, a new path metric update scheme is proposed based on two techniques, named swapped state grouping and swapped computing. The proposed scheme leads to a simple interconnection consisting of 2×2 switches

Published in:

Electronics Letters  (Volume:37 ,  Issue: 14 )